Onethinx Creator Projects

Hello All,

I am a bit confused about the Onethinx Creator example projects. For my current and previous projects, I edited the Top Design in PSoC Creator, generated the application, then used the UDB porting tool to copy the relevant files into the VSCode project. However, each Creator Example Project has a PSoC Creator project folder already inside the VSCode project folder.

If I edit the top design in one of these example projects, do I have to run the UDB porting tool or do something special to make the whole project build in VSCode?

Paul

Hi Paul,

With Onethinx Creator you no longer have to run the porting tool. What you need to do is to successfully build the design in PSoC Creator and do a Clear-Reconfigure in VSCode before you can use the generated API.

Furthermore, you no longer need to write UDBinit(); or any other init. It takes care of itself. VSCode accesses the nested Generated Source folder of PSoC Creator automatically.

So you make your Top Design, assign the pins, build in PSoC Creator, Clear-Rebuild in VSCode, write your program, Build in VSC, Launch, Enjoy!

Tom

Hi Tom,

Thanks for the info.

I do have a question about clock settings in PSoC Creator and their effect on the module. If clock settings in PSoC Creater conflict with those set by the locked M0+ core, which one wins?

The reason I ask is because I need the ADC clock to be more accurate than one derived from the IMO. I would like to use the BLE ECO (Alt_HF) for this purpose.

I can write code to get many clock and mux path settings, but I can not find APIs to read status/settings for the BLE ECO. So, in this respect, I am “flying blind”.

Would it be possible to get a list of clocks and other resources that I should not mess with?

Paul

Hi Paul,

Great question, it reminded me…

The M4 clock settings take over. And there are clock settings that can brick the module, however, we have included a delay of 1.5 seconds before the “main” starts. This delay is located in:

Onethinx_Creator.cydsn\Generated_Source\PSoC6\cyfitter_cfg.c

in function Cy_SystemInit(void)

This Delay is added automatically when you build the project in PSoC Creator, and you should remove it in the release version. The delay is put above Clock_Init on purpose!

If there is no delay and you play with different frequencies, and brick the module, there will be no time for your programer to accquire the module, and reprogram it to unbrick it. With the delay, there is 1.5s delay after restart, before it gets bricked, so the programmer can aquire it.

Your project may not have the new “CoreStripper” that automatically adds this functionality. You can download the “new” examples from our github and just replace the CoreStripper.exe in your project, with the new CoreStripper found in the new project on github.

Alternatevly, if you dont want it to create the delay all the time, you can add the delay yourself in the same location, and use the old CoreStripper, although we do not recommend it.

Feel free to mess around with the clocks as long as there is the Delay before Clock_Init

Tom

You can also adjust clocks and paths here:

Thanks for the info. Now I have a couple more questions.

  1. What causes the core stripper to run? Clean configure? Build? Something else?
  2. Quite some time ago, I was told that the stack used the Watch Crystal Oscillator (WCO) for timing. Is this still true?

Paul

  1. Build causes CoreStripper to run. (not exactly sure how it works in the background)
  2. WCO is used for timing

Hi Tom,

I just looked in the file OnethinxCore01.h for stack BF. In the Core Revision section, the comment for stack BF reads Changed RX timing window to SysTick timer (32MHz instead of 32KHz). So it appears that some clock other than the WCO is needed by the stack.

I want to avoid messing up the stack timing. Could you tell me what clock drives the M0+ SysTick timer?

Paul

Hi Paul,

WCO is used for RTC, so for LoRaWAN_Sleep and LoRaWAN_GetTime/SetTime

BLE_ECO is used for stack timings like RX windows.

As I said, you wont mess it up if you have the CyDelay(1500); in front of the clock init and you can experiment as much as you want. If you are then happy with it and it works, you can remove the CyDelay.

Tom

Hi Tom,

Thanks for the info. Now I’m going to ask one more question.

Since the only API available for the BLE ECO are start and stop functions, I can’t read the configuration that was used for startup. I would like to use the AltHF (BLE ECO) clock for the ADC, so I can get a more precise sampling rate. So, I need to know what I have to work with. If you could give me the startup parameters, I’d appreciate it.

Paul

To clarify, what I am asking for are the configuration values that were passed to Cy_BLE_EcoStart().

Paul

Hi Paul

Are you using ADC in PSoC Cretor?
image

You can make ADC use external terminal
image

Then add AltHF BLE ECO according to this config

image

And add clock to ADC

This will allow you to have 16MHz clock on the ADC instead of 4MHz.

Try it with CyDelay before ClockInit and let me know! Hope this helps

Tom

So, are you saying that the BLE ECO Frequency is 32 MHz and the BLE ECO Clock Divider is 1?