coreConfig.System.Idle.DebugOn is set to false, you are able to brick a module. This is what happens when the DebugOn is set to false:
- Device resets, M0+ starts
- M0+ enables the debug port
- M4 starts
- M4 initializes stack using LoRaWAN_Init(&coreConfig);
- M0+ disables debug port
Now the time between 2. and 5. is very short if no delay is put at 3. (probably a few microseconds).
A few microseconds is not enough for the debugger to get attached to the chip. Therefor, adding a delay of 1 or 2 seconds before anything else wil allow a safe margine the debugger to access the chip.
This delay can be removed for a final version, which you don’t need to debug anymore. You can do other functions as long as the debug port isn’t disabled within 1 second from start.
I’m still checking with Cypress as I believe I am able to connect using the Testmode Acquire with the PSoCProgrammed CLI. I guess clearing the flash with the CLI can recover, I’m still waiting for Cypress to answer.