Clock configuration Modus Toolbox 1.1

Tools (IDE, programmer etc.)
1

Hi all,

The clock configuration below is valid for Modus Toolbox 1.1?

Blockquote
CLOCKS

Platform clocks are set for high performance (144 MHz CLK_FAST for CM4 core
and 72 MHz CLK_SLOW for CM0+) but with a peripheral-friendly CLK_PERI
frequency (72 MHz).

FLL (Frequency-Locked Loop) Disabled
PLL (Phase-Locked Loop) Enabled
Source: IMO (8 MHz)
Frequency: 144 MHz
CLK_HF0
Source: CLK_PATH1 / PLL (144 MHz)
CLK_FAST (CM4 clock)
Source: CLK_HF0 (144 MHz)
CLK_PERI (peripheral clock):
Source: CLK_HF0 (144 MHz)
Divider: 2
Frequency: 72 MHz
CLK_SLOW (CM0+ clock):
Source: CLK_PERI (72 MHz)

Blockquote

2

Hi!

You can disable the clock section to let the clock run at default speed. Is this okay or do you want a high speed clock?

Loot at our github for the example with default clock speed.

3

Hello All,

I’m confused about the clocking situation. I’ve set clocks and dividers in my project to set A/D sampling rate and UART Baud rate. However, I’ve found that the UART at half the rate it should be. I’ve check the configurator setup and found nothing wrong. So now I suspect that the M0+ core is changing some of my settings.

Does the M0+ code set any system/peripheral clocks? If so, could someone tell me what clocks it sets and what clock settings are required?

Paul

4

Hi Paul,

Which stack revision are you having?

This is our configuration since 0xB0 (which is done on the M0+):

static void ClockInit(void)
{
	uint32_t status;

	/* Enable all source clocks */
	status = Cy_SysClk_WcoEnable(500000u);
	if (CY_RET_SUCCESS != status)
	{
		CyClockStartupError(CYCLOCKSTART_WCO_ERROR);
	}
	Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
	
	Cy_BLE_EcoStart(&bleCfg);
	
	/* Configure CPU clock dividers */
	Cy_SysClk_ClkFastSetDivider(0u);
	Cy_SysClk_ClkPeriSetDivider(0u);
	Cy_SysClk_ClkSlowSetDivider(0u);

	/* Configure LF & HF clocks */
	Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH0);
	Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE);
	Cy_SysClk_ClkHfEnable(0u);

	/* Configure Path Clocks */
	Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_IMO);
	Cy_SysClk_ClkPathSetSource(2, CY_SYSCLK_CLKPATH_IN_IMO);
	Cy_SysClk_ClkPathSetSource(3, CY_SYSCLK_CLKPATH_IN_IMO);
	Cy_SysClk_ClkPathSetSource(4, CY_SYSCLK_CLKPATH_IN_IMO);
	Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_IMO);

	/* Configure miscellaneous clocks */
	Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV);
	Cy_SysClk_ClkTimerSetDivider(0);
	Cy_SysClk_ClkTimerEnable();
	Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0);
	Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_NO_DIV);
	Cy_SysClk_ClkPumpEnable();
	Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
	Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);

	/* Disable clocks started by default */
	Cy_SysClk_IloDisable();

	/* Set memory wait states based on 8 MHz HFClk[0] */
	Cy_SysLib_SetWaitStates(false, 8);
}

Which means that the peripheral clock is running at 8MHz.

ModusToolbox should update the clocks however, not sure why this is going wrong.

Can you check if the periperal clock is updated?

5

Rolf,

Thanks for the information. Honestly, the Modus Toolbox and VSCode environments, combined with the complexity of the PSoC 6, make me feel like a monkey banging on the keyboard. And I’ve done plenty of work with PSoC 1, 4, & 5. The design.modus file was probably correct before I messed with it, not fully understanding what I was doing.

I believe much of my misunderstanding comes from the fact that the stack is secret and the M0+ core is locked down. You certainly have the right to protect your stack code from theft, but the secrecy does make it risky when common resources are used.

I think it would be helpful to other programmers and me if someone could publish (perhaps in the module specification document) what resources need to be left alone, and the required settings/configuration of these resources.

I will study the code you just posted, along with an unaltered ModusToolbox2.0_HelloWorld design.modus file to set the clocks the way they need to be. If I have any questions, you’ll hear from me.

Paul

6

Rolf,

It looks like the M0+ core is doing more to the clock system than shown in the code you posted. I wrote some code to fetch configuration information. Here’s what I found:

  • CLK_PATH0 source is ALTHF, not IMO
  • The FLL is enabled and multiplying by 12.5.
  • CLK_PERI divider is 1, not 0 (i.e. divides by 2)

So, CLK_PERI frequency is 6.25 x ALTHF frequency. Assuming that ALTHF frequency is 8 MHz, CLK_PERI would be 50 MHz. This is consistent with my most recent UART test. In order to receive data supposedly sent at 9600 baud, I had to set my PC’s serial port to 57600 baud (9600 x 6).

I should mention that my stack version is B0. A co-worker has a kit with B4 on it. I’ll put it through the same test.

Paul

7

Update:
After running the same code on a kit with a B4 stack, the configuration was the same as shown in the code snippet.

  • CLK_PATH0 source is IMO
  • FLL is disabled
  • CLK_PERI divider is 0 (i.e. divides by 1)

As soon as my new modules arrive, I can update my kit. I hope there won’t be too many more changes like this between stack versions.

Paul

8

OK. Now I understand the clocking situation. While I await the arrival of modules with the newer stack, I would like to operate my B0 module with the same clocks as the new one, if it doesn’t cause trouble. So, I have two questions:

  • Should the B0 module function correctly with the new (slower) clock speeds?
  • When does the ClockInit() function on the M0+ get executed? More importantly, does it occur before the main() function on the M4? Or do I need to wait awhile before I try to change the clocks in my code?

Paul

9

Hi Paul,

Yes, the B0 module will work with lower clock speeds as well. Timing for the stack is derived from the WCO RTC. The stack will set up the code for this internally (no need to enable the WCO/RTC if you need it).

The ClockInit() function is executed before the M4 main() function (it is executed before the M4 starts), so no need to wait for the clocks.

And yes, clock setting for the more recent version of the stack is IMO/1 (8MHz) for the Peri clock, the M4 clock and the M0+ clock.